The present invention generally relates to high performance transistor devices, and more specifically to low threshold voltage, high performance MOS transistors having buried regions of increased dopant concentration located below the transistors--channel regions.
As MOS technology has evolved, the supply voltage (Vdd) has scaled with the size of the devices. For example, CMOS transistors having channel region widths in the range of 2 .mu.m are provided with 5 volt supply voltages, whereas transistors having channel region widths in the range of 0.5 .mu.m are provided with 3.3 volt supply voltages. As channel region widths decrease to 0.35 .mu.m and 0.25 .mu.m, the supply voltages correspondingly decrease to 2.5 and 1.8 volts. For many applications, it would be desirable to provide lower supply voltages for given device sizes. This is because devices requiring lower supply voltages generally conserve power, a feature which is especially desirable in systems which dissipate large amounts of energy or rely on limited power sources such as batteries. However, there has been some concern about the effect of low Vdd on device performance.
In circuits made up of conventional MOS devices, the relationship of maximum frequency f.sub.max to supply voltage and threshold voltage is governed by long and short channel effects of the component devices. As expected, for longer channel devices, the long channel effects predominate and for shorter channel devices, the short channel effects predominate. Most devices exhibit some characteristics of both, with devices having channel lengths between one and two micrometers exhibiting both characteristics about equally. The maximum frequency of circuits comprised of truly long channel devices is given by: EQU .function..sub.max .alpha.(V.sub.dd -V.sub.t).sup.2 /V.sub.dd
The same parameter for circuits made up of truly short channel devices is given by: EQU .function..sub.max .alpha.(V.sub.dd -V.sub.t)/V.sub.dd =t-V.sub.1 /V.sub.dd
From these equations, it is apparent that the performance (frequency) of a circuit made up of truly long channel devices is dependent upon the absolute value of the supply voltage. Thus, if the supply voltage to the devices in such circuits is lowered, performance is also lowered. However, in circuits comprised of truly short channel devices, performance is governed by the ratio of threshold voltage to supply voltage (Vt/Vdd). This means that in such circuits the supply voltage to the devices can be lowered with no loss in performance, f.sub.max, so long as the ratio Vt/Vdd is kept constant. For many devices, this relation is nearly true, and it becomes exactly true for devices in which the saturation voltage scales with the supply voltage.
Although low Vt short channel devices appear attractive for the above reason, special problems have been observed with such devices. First, as Vt is lowered, the leakage current of the transistor--which is the current flowing across the channel region when the transistor is off--increases. For some applications in which the device must frequently switch (e.g., microprocessors), this is not a problem. However, for applications in which the device is normally inactive (e.g., memory devices), the leakage current can cause the device to be quite energy inefficient. Regardless of whether the leakage current represents a significant problem, another problem has been observed with very short channel devices having low thresholds. Specifically, if the distance between the source and drain regions becomes too small, the depletion, regions in the channel region adjacent the source and drain can overlap to cause punch through. When this occurs, current flows through the path created by depletion region, even when the transistor is turned "off" (i.e., the gate voltage does not exceed the threshold voltage).
In high threshold voltage devices, it is known that a "buried electrode region" or "ground plane" may be employed to suppress growth of depletion regions in the channel region and thereby prevent punch through. Such devices are described in an article by R. H. Yan, et al., "High Performance 0.1 .mu.m Room Temperature Si MOSFETs," 1992 Symposium on VLSI Technology Digest of Technical Papers, pages 86-87, which is incorporated herein by reference for all purposes. Briefly, a buried electrode region is a region of relatively high dopant concentration extending underneath the channel region and having the same conductivity type as the device's bulk or well region. Unfortunately, it was not clear from this work whether such buried electrode regions could have beneficial application in low threshold devices, and if so, how the buried electrode regions could be optimally incorporated into such devices.
What is needed is an improved high performance, short channel transistor device having a low threshold voltage and protection from punch through.